# Appendix A: Core Board - Neon Pixel Edition

## Core Board - Neon Pixel Edition Design

The **v0.4 Core Board (CB) - Neon Pixel Edition** includes support for the four user-configurable hall sensors (under the M - + S symbols at the bottom edge). It also supports an ambient light sensor (upper left), but that is not needed for the Neon Pixels because they do not have the insanely wide dynamic range as the LED array. [The complete CB schematic is here](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/Neon_Pixels_Working_In_3_Modes/Electronic%20Design/Core64%20CB%20v0.4-NP/Core64%20CB%20v0.4-NP%202020-11-25%20Schematic.pdf). This varient only supports a single core plane versus the standard v0.4 CB which supports up to eight.

![](https://699013105-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MQdPFfouM2ulKSFIJJM%2F-MQynYW2YGO0qSxTOUgK%2F-MQyoSO0b6FauppqGZuX%2FIMG_2648%20Neon%20Pixel%20Heart.jpeg?alt=media\&token=9b920065-a2fd-41c8-a53d-006b8a50103d)

{% hint style="info" %}
The Neon Pixels are designed by Pierre Muth with details [here on his blog](https://pierremuth.wordpress.com/2020/07/08/neon-pixel/). As of this writing, they are not a product that is offered for sale, so you'll need to make your own. There is a  [repository on Github for the Neon Pixels](https://github.com/pierre-muth/NeonPixel) too.
{% endhint %}

## Connections to Logic Board

The Neon Pixel backplane connects to 4 pins on the Logic Board (LB) at the lower header which was designed for an LCD. It uses the SPI BUS.

![LCD Header](https://699013105-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MQdPFfouM2ulKSFIJJM%2F-MQyZtL2nbyQoYrFtme9%2F-MQyhOyqxVb6pB3tOw7l%2FLB%20TFT%20Header%20Render.png?alt=media\&token=99f5a015-b001-43ec-9f8e-c05b6face365)

The schematic layout is in the same position as the header is physically placed on top of the the LB. Only four connections are needed, numbered from left to right.&#x20;

| Header Pin #  | Description                     |
| ------------- | ------------------------------- |
| 1             | GND, Ground                     |
| 2             | 5V0, Output of the 5V regulator |
| 4             | CLK, Clock                      |
| 6             | SDO, Data Out from MCU          |
| 7  (optional) | CS, Chip Select                 |

The schematic shown below for the LB is an excerpt from [the complete LB schematic here](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/master/Electronic%20Design/Core64%20LB%20v0.4/Core64%20LB%20v0.4%202020-11-19%20As%20Fabricated%20Schematic.pdf). The [v0.4 LB Errata is here](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/master/Electronic%20Design/Core64%20LB%20v0.4/Core64%20LB%20v0.4%20Errata.pdf).

![SPI pins available for Neon Pixels](https://699013105-files.gitbook.io/~/files/v0/b/gitbook-legacy-files/o/assets%2F-MQdPFfouM2ulKSFIJJM%2F-MQyZtL2nbyQoYrFtme9%2F-MQyjCGIxDsjlyvYEURo%2FSchematic%20LCD%20pins%20for%20Neon%20Pixels.png?alt=media\&token=ba26736b-1fbb-4bad-b63b-bad1eaa8d6f8)

## Firmware

Firmware to support Neon Pixels along with the LED Array is in [this release](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/releases/tag/Neon_Pixels_Working_In_3_Modes) on Github.

The Neon Pixels are enabled in the firmware [here](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/Neon_Pixels_Working_In_3_Modes/Firmware%20Source%20Code/Core-64-Interactive-Core-Memory-Badge/HardwareIOMap.h#L41).

The "Application Layer" of the code that drives the Neon Pixel behavior through three modes of operation starts [here](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/Neon_Pixels_Working_In_3_Modes/Firmware%20Source%20Code/Core-64-Interactive-Core-Memory-Badge/Core-64-Interactive-Core-Memory-Badge.ino#L188).

The API is in [Neon\_Pixel\_HAL.h](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/Neon_Pixels_Working_In_3_Modes/Firmware%20Source%20Code/Core-64-Interactive-Core-Memory-Badge/Neon_Pixel_HAL.h) and driver which moves pixel data array out through the SPI bus is down in src/NeonPixel/[NeonPixel\_Driver.h](https://github.com/ageppert/Core-64-Interactive-Core-Memory-Badge/blob/Neon_Pixels_Working_In_3_Modes/Firmware%20Source%20Code/Core-64-Interactive-Core-Memory-Badge/src/NeonPixel/NeonPixel_Driver.h).
